1. Field of the Invention
The present invention relates to a timing signal generating apparatus capable of generating a timing signal delayed relative to a reference clock signal for a time longer than a period of the reference clock signal.
2. Description of the Prior Art
For having a better understanding of the present invention, a hitherto known timing signal generating circuit will be described in some detail by referring to FIGS. 3 and 4 of the accompanying drawings.
In FIG. 3 which shows a general arrangement of a hitherto known timing signal generating apparatus, a reference numeral 11 denotes a change-over circuit, a numeral 12 denotes a setting circuit, numerals 13a and 13b denote counters, respectively, numerals 14a and 14b denote coincidence detection circuits, respectively, a numeral 15 denotes a gate circuit, numerals 16a to 16c denote input terminals, respectively, and a reference numeral 16d denotes an output terminal.
The timing signal generating apparatus shown in FIG. 3 is designed to derive a timing signal 20 which is delayed relative to a reference clock signal 17 for a time longer than the period of the reference clock signal 17. To this end, each of the counter 13a and 13b is placed with predetermined delay time data for thereby allowing the timing signal to be generated with a delay of the abovementioned duration relative to the reference clock signal 17 by counting clock pulses 19.
Operation of the timing signal generating apparatus shown in FIG. 3 will be elucidated by referring to a timing chart illustrated in FIG. 4.
Applied to the input terminal 16a is the reference clock signal 17 shown in FIG. 4 at (a), while a timing data signal 18 shown in FIG. 4 at (b) is applied to the input terminal 16b. The timing data signal 18 represents address designation information supplied to the setting circuit 12 where the output data to be loaded in the counters 13a and 13b are stored, as described hereinafter. The input terminal 16c is supplied with the clock pulses 19 for the counters 13a and 13b. The timing signal 20 shown in FIG. 4 at (h) is derived from the output terminal 16d.
The reference clock signal 17 serves to determine the period of the timing data signal 18. More specifically, the period of the reference clock signal 17 is equal to the period or time interval at which the timing data signal 18 is changed over.
The clock pulse signal 19 has a period shorter than that of the reference clock signal 17 and is applied to the counter 13a and 13b.
The change-over circuit 11 operates to apply alternately the reference clock signal 17 to the counters 13a and 13b. The setting circuit 12 serves to load the output data C and C1 shown in FIG. 4 at (c) to the counters 13a and 13b, which data C and C1 are previously stored in the setting circuit 12 at the locations designated by the timing data signal 18.
In response to the reference clock signal 17 applied through the change-over circuit 11, the counter 13a is placed with the output data C or C1 supplied from the setting circuit 12.
A signal shown in FIG. 4 at (d) corresponds to the reference clock signal 17a shown in FIG. 4 at (a) and derived through the change-over circuit 11 and is a applied to the counter 13a. The signal shown in FIG. 4 at (d) serves to load the output data C shown in FIG. 4 at (c) in the counter 13a. The latter counts the clock pulses 19 in a number corresponding to the output data C.
Shown in FIG. 4 at (e) is a waveform of the output signal of the coincidence detection circuit 14a which is produced when the output signal representative of the content of the counter 13a becomes "0" level.
Shown in FIG. 4 at (f) is a signal which corresponds to the reference clock signal 17b derived through the change-over circuit 11 and is applied to the counter 13b.
The signal shown in FIG. 4 at (f) serves to place the output data C1 shown in FIG. 4 at (c) in the counter 13b which counts the clock pulses 19 by a number corresponding to the output data C1.
Shown in FIG. 4 at (g) is a signal waveform which is outputted from the coincidence detection circuit 14b when the content of the counter 13b becomes "0".
By way of example, it is assumed that the period of the reference clock signal 17 shown in FIG. 3 is 1 mS (millisecond) and that of the clock pulse 19 is 1 .mu.S. On the assumption, in order to derive the timing signals shown in FIG. 4 at (e) and (g) which are delayed for 1.3 mS relative to the reference clock signals 17a and 17b, respectively, it is required that such data be previously stored in the setting circuit 12 that the output data C and C1 shown in FIG. 4 at (c) represent, respectively, a value "1300" which corresponds to the delay time or lag of 1.3 mS.
As will be appreciated from the foregoing description, in order that the hitherto known timing signal generating apparatus can generate the timing signal delayed relative to the reference signal 17 for a time longer than the period of the latter, the use of the additional counter 13b is indispensable because the reference clock signal succeeding to the one which has triggered the counting operation of the counter 13a makes appearance in the course of the counting operation of the latter 13a, to involve expensiveness in implementation of the timing signal generating apparatus. Another disadvantage of the hitherto known timing signal generating apparatus shown in FIG. 3 is seen in the fact that with two loops each including the counter and the coincidence detection circuit, it is only possible to generate the timing signal delayed to the reference clock signal 17 for a time which is not longer than a sum of two periods of the reference clock signal 17. Of course, the circuit arrangement shown in FIG. 3 may be so modified that the timing signal can be generated with a delay of magnitude greater than two periods of the reference clock signal. To this end, however, the number of the sets of the counter and the coincidence detection circuit must be increased, which means that the circuit arrangement becomes correspondingly complicated, thus giving rise to a problem.